Copyright(C) 1994,1995,1996,1997 Terumasa KODAKA , Takeshi KONO
■GOLDEN GATE chipset
Target PC-9821Nf
Chip GOLDEN GATE
Description o GOLDEN GATE is a chipset for PICO|POWER's Pentium processor, and controls the bus, clock, second cache, etc. around the Pentium processor.
o The PC-9821Nf uses the GOLDEN GATE chipset along with the RED WOOD chipset, also from PICO|POWER.
o GOLDEN GATE chipset uses the same I/O 0900h,0906h as RED WOOD chipset. Access to these I/O addresses is made to the RED WOOD chipset for
word access, and to the GOLDEN GATE chipset for byte access. Therefore, access to the GOLDEN GATE chipset must be byte access.
o The various registers of the GOLDEN GATE chipset are set for operations related to the fundamentals of the machine, so the values set by
the ITF should not normally be changed.
Related I/O 0900h(WORD)
I/O 0906h(WORD)
I/O 0900h(BYTE)
Name GOLDEN GATE (INDEX)
Target PC-9821Nf
Function
[READ/WRITE]
bit 7～4: Reserved (set to 0000b)
bit 3～0: INDEX
* Select register to read/write with I/O 0906h.
Description o Select the register to read and write in the GOLDEN GATE chipset.
Related I/O 0906h(BYTE)
I/O 0906h(BYTE)
Name GOLDEN GATE (DATA)
Target PC-9821Nf
Function
[READ/WRITE]
bit 7～0: DATA
--------+-------------------------------------------------
INDEX | Name
--------+-------------------------------------------------
00h | RESET Sampled Register A
| bit 7: CPU Bus Pipelining Disable
| 1=Enable
| 0=Disable
| bit 6: Reserved
| bit 5: L1 WriteBack/WriteThrough Select
| 1=WriteBack
| 0=WriteThrough
| bit 4〜2: Clock Skew Adjust
| --------+-----------+--------------
| | Delay(ns) | Tolerance(ns)
| --------+-----------+--------------
| 000b | 0 | ±0.5
| --------+-----------+--------------
| 001b | -0.55 | ±0.25
| --------+-----------+--------------
| 010b | -1.1 | ±0.5
| --------+-----------+--------------
| 011b | -1.65 | ±0.75
| --------+-----------+--------------
| 100b | +0.55 | ±0.25
| --------+-----------+--------------
| 101b | +1.1 | ±0.5
| --------+-----------+--------------
| 110b | +1.65 | ±0.5
| --------+-----------+--------------
| 111b | +2.20 | ±1.0
| --------+-----------+--------------
| * 000b is set for PC-9821Nf
| bit 1,0: Reserved
--------+-------------------------------------------------
01h | RESET Sampled Register B
| bit 7,6: L2 Cache Read Follow-on Clocks
| 00b=1 clock
| 01b=2 clocks
| 10b=3 clocks
| 11b=Reserved
| * 00b is set for PC-9821Nf
| bit 5,4: L2 Cache Read Lead-off Clocks
| 00b=2 clocks
| 01b=3 clocks
| 10b=4 clocks
| 11b=Reserved
| * 00b is set for PC-9821Nf
| bit 3: L2 Cache Type
| 1=Asynchronous
| 0=Synchronous
| * 1 is set for PC-9821Nf
| bit 2,1: L2 Cache Size Select
| 00b=Reserved
| 01b=256KB
| 10b=512KB
| 11b=1MB
| * 01b is set for PC-9821Nf
| bit 0: L2 Cache Disable
| 1=Disable
| 0=Enable
--------+-------------------------------------------------
02h | RESET Sampled Register C
| bit 7,6: L2 Cache Read Follow-on Clocks
| 00b=1 clock
| 01b=2 clocks
| 10b=3 clocks
| 11b=Reserved
| * 00b is set for PC-9821Nf
| bit 5,4: L2 Cache Write Lead-off Clocks
| 00b=2 clocks
| 01b=3 clocks
| 10b=4 clocks
| 11b=Reserved
| * 00b is set for PC-9821Nf
| bit 3: SAMPLEN
| 1=Use defaults for configuration
| 0=Sample LA bus pins on RESET
| bit 2～0: Write Buffer Enable
| 111b=Disable
| 110～001b= Reserved
| 000b=Enable
| * 111b is set for PC-9821Nf
--------+-------------------------------------------------
03h | RESET Sampled Register D
| bit 7～5: Reserved
| bit 4: SMI L2 Cache enable
| 1=Enable L2 in SMM
| 0=Disable L2 in SMM
| bit 3: Disable L1 Cache
| 1=Disable
| 0=Enable
| bit 2〜0: Reserved
| * Configure various cache settings.
--------+-------------------------------------------------
04h | Throttling Modulation Frequency
| bit 7～4: Reserved
| bit 3: Clock Throttling Enable
| 1=Enable
| 0=Disable
| bit 2〜0: Throttling Modulation Frequency
| --------+---------------+----------------------
| | CPUCLK | Modulation Period
| | Divided by | with CPU @50MHz
| --------+---------------+----------------------
| 000b | 800 | 16μs
| 001b | 1600 | 32
| 010b | 3200 | 64
| 011b | 6400 | 128
| 100b | 12800 | 256
| 101b | 25600 | 512
| 110b | 100000 | 2ms
| 111b | 40000 | 8ms
| --------+---------------+----------------------
--------+-------------------------------------------------
05h | Throttle Control Register B
| bit 7〜4: Clock Throttling Duty Cycle, Ten's Digit
| 0000〜1001b= 0-9 Decimal Ten's Digit
| 1010〜1111b= Reserved
--------+-------------------------------------------------
06h | Thermal Throttling Modulation Frequency
| bit 7〜5: Reserved
| bit 4: Thermal Throttle Lock
| 1=Lock
| 0=Unlock
| bit 3: Thermal Throttling Enable
| 1=Enable
| 0=Disable
| bit 2〜0: Thermal Throttling Modulation Frequency
| --------+---------------+---------------------
| | CPUCLK | Modulation Period
| | Divided by | with CPU @50MHz
| --------+---------------+---------------------
| 000b | 800 | 16μs
| 001b | 1600 | 32μs
| 010b | 3200 | 64μs
| 011b | 6400 | 128μs
| 100b | 12800 | 256μs
| 101b | 25600 | 512μs
| 110b | 100000 | 2ms
| 111b | 40000 | 8ms
| --------+---------------+---------------------
--------+-------------------------------------------------
07h | Thermal Control Register B
| bit 7〜4: Thermal Throttling Duty Cycle, Ten's Digit
| 0000〜1001b= 0-9 Decimal Ten's Digit
| 1010〜1111b= Reserved
--------+-------------------------------------------------
08h | VL Stop Clock Register
| bit 7〜1: Reserved
| bit 0: CPU Full STPCLK# Enable
| 1=VLCLK pin disabled
| 0=VLCLK pin enabled
| * Set whether to stop CPUCLK. 01h is set for PC-9821Nf.
--------+-------------------------------------------------
09h | Misc. Configuration Register
| bit 7: Reserved
| bit 6: TAG Initialization
| 1=Force Read Misses and allow TAG and SRAM to be written
| 0=Normal Operation
| bit 5,4: Reserved
| bit 3: Synchronous SRAM Clock PowerManagement Enable
| 1=L2 Cahce clock on all the time
| 0=L2 Cache clock stopped on all bus idle cycles
| bit 2: Reserved
| bit 1: x8 TAG Compare
| 1=enable
| 0=disable
| bit 0: Reserved
| * Configure various settings for the second cache. 02h is specified for PC-9821Nf.
--------+-------------------------------------------------
0Ah | Reserved
0Bh | Reserved
--------+-------------------------------------------------
0Ch | Cacheability Override Bits
| bit 7: DC000~DDFFFh
| bit 6: DA000~DBFFFh
| bit 5: D8000~D9FFFh
| bit 4: D0000～D7FFFh
| bit 3: CC000～CFFFFh
| bit 2: C8000~CBFFFh
| bit 1: C4000～C7FFFh
| bit 0: C0000~C3FFFh
| 1=Do not cache
| 0=Allow caching
| * Set cache permission/prohibition for each specified area. FFh is specified for PC-9821Nf.
--------+-------------------------------------------------
0Dh | Cacheability Override Bits
| bit 7: DE000～DFFFFh
| bit 6: E4000～E7FFFh
| bit 5: E8000～EBFFFh
| bit 4: EC000~EFFFFh
| bit 3: F0000～F3FFFh
| bit 2: F4000～F7FFFh
| bit 1: F8000～FFFFFh
| 1=Do not cache
| 0=Allow caching
| bit 0: Reserved
| * Set cache permission/prohibition for each specified area. E0h is set for PC-9821Nf.
--------+-------------------------------------------------
0Eh | Cacheability Override Bits
| bit 7～4: Reserved
| bit 3: A27
| bit 2: A26
| bit 1: A25
| bit 0: A24
| 1=Do not cache
| 0=Allow caching
| * Set enable/disable caching at addresses higher than the specified address bit. 00h is set for PC-9821Nf.
--------+-------------------------------------------------
0Fh | Stepping ID Register
| bit 7〜4: Stepping ID of Production part
| 0000b=Prototype
| 0001b=A0 silicon
| bit 3〜0: Stepping ID of Prottype part
| 0000b=X0 Silicon
| 0001b=X1 silicon
| 0010b=X2/X3/A0 Silicon
| * Indicates the revision of the GOLDENGATE chipset. One lot of PC-9821Nf returned 12h.
--------+-------------------------------------------------
* Read and write registers set by I/O 0900h
Description o Read and write various registers of GOLDEN GATE chipset.
Related I/O 0900h(BYTE)